`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:50:08 08/20/2013
// Design Name:   coprocessor0
// Module Name:   C:/Users/James/Dropbox/Uni/FYP/uofa-mips/BoardSystem/coprocessor_tb.v
// Project Name:  BoardSystem
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: coprocessor0
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module coprocessor_tb;

	// Inputs
	reg clk;
	reg reset;
	reg [5:0] interrupts;
	reg [7:0] registerAddress;
	reg writeEnable;
	reg [31:0] writeData;
	reg [31:0] pc;
	reg eret;
	reg overflowAble;
	reg overflow;
	reg addressErrorOnLoadAble;
	reg addressErrorOnLoad;
	reg addressErrorOnStoreAble;
	reg addressErrorOnStore;
	reg badInstruction;

	// Outputs
	wire [31:0] readData;
	wire CP0Jump;

	// Instantiate the Unit Under Test (UUT)
	coprocessor0 uut (
		.clk(clk), 
		.reset(reset), 
		.interrupts(interrupts), 
		.registerAddress(registerAddress), 
		.writeEnable(writeEnable), 
		.writeData(writeData), 
		.pc(pc), 
		.eret(eret), 
		.overflow(overflow), 
		.addressErrorOnLoad(addressErrorOnLoad), 
		.addressErrorOnStore(addressErrorOnStore), 
		.badInstruction(badInstruction), 
		.readData(readData), 
		.CP0Jump(CP0Jump)
	);

	always
	begin
		clk = 1;
		#10;
		clk = 0;
		#10;
	end
	
	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		interrupts = 0;
		registerAddress = 0;
		writeEnable = 0;
		writeData = 0;
		pc = 0;
		overflow = 0;
		addressErrorOnLoad = 0;
		addressErrorOnStore = 0;
		badInstruction = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

        // check it jumps, check it accepts invalid signal, check eret (correct pc, flushes), overflow, check mfc0
        // ^^^^^^^ probably need to fix the initialisation above here too
		  
		 
		interrupts = 1;
		#20;
		interrupts = 0;
		#20;
		
		interrupts = 1;
		#20;
		interrupts = 0;
		#20;
		
		interrupts = 1;
		#20;
		interrupts = 0;
		#20;
		
		interrupts = 1;
		#20;
		interrupts = 0;
		#20;
		
		interrupts = 1;
		#20;
		interrupts = 0;
		#20;
		

	end
      
endmodule

